1. Field of the Invention
The present invention generally relates to memory systems. More particularly, the present invention relates to memory controllers adapted to handle memory read return data from different time domains of memory devices.
2. Discussion of the Related Art
Current and future dynamic random access memory (DRAM)-based memory subsystems employ high-speed interfaces, commonly referred to as a channel, to transmit data (both address/commands and data to be written to the DRAM) and to receive data being read. As the frequency of these interfaces to the memory subsystem increase, the number of clock periods required to traverse the physical implementation of the memory subsystem's communication channel becomes greater than one. This configuration means that multiple time domains exist in the communication channel.
In other words, a memory controller may be connected via the communication channel to, for example, a plurality of DRAM ranks, each being a different physical distance away from the memory controller. A DRAM rank is defined as all of the DRAM devices connected to the same select signal. Because of the different distances for each DRAM rank connected to the communication channel, the time for an issued command to be received by a DRAM rank is different for each DRAM rank connected to the communication channel, as the DRAM ranks closer to the memory controller would receive the command earlier than those positioned further away. That is, the command signal takes more time to travel down the communication channel to the DRAM ranks located further away from the memory controller than those located closer.
DRAM ranks may be connected to the communication channel at a different location. Therefore, each DRAM rank may have a different time domain. For example, it may take one clock cycle for DRAM rank A to receive a command from the memory controller, two clock cycles for DRAM rank B to receive a command from the memory controller, and three clock cycles for DRAM rank C to receive a command from the memory controller. In this example configuration, DRAM rank B is twice as far from the memory controller as DRAM rank A, and DRAM rank C is three times further from the memory controller as DRAM rank A.
If multiple time domains existing in the communication channel are not accounted for, it is possible that read commands issued from the memory controller, for example, may result in memory read return data to be transmitted to the memory controller “out-of-order” from the order the read commands were originally issued. That is, a read command subsequently issued to a DRAM rank closer to the memory controller than one previously issued to a DRAM rank located further away may result in the memory read return data from the closer DRAM rank arriving at the memory controller before the memory read return data from the further DRAM rank.
Moreover, even though read commands may be issued sequentially from the memory controller to the different DRAM ranks located at different locations from each other, memory read return data may be transmitted from different DRAM ranks back to the memory controller so that they arrive at the same time, thereby causing a “data collision”. Memory controllers are typically not adapted to handle receipt of out-of-order memory read return data. Data collisions cause corruption of the data, making the received “collided” data unusable.
Adding pipeline stages to a DRAM device's data return path is one way to “levelize” the channel by building “delay” into the DRAM devices so as to minimize the effects of multiple time domains existing in the communication channel. That is, “levelization” is a process by which pipeline delay is added to DRAM devices closer in position to the memory controller so as to make all data returns take the same amount of time, regardless of their distances from the memory controller. However, adding pipeline stages increases the complexity of the DRAM device, not to mention increasing their costs of production. Moreover, because levelization prevents out-of-order data returns from occurring, out-of-order handling features found in some memory controllers, which allow an increase in data bus efficiency and a reduction in latency, would be wasted.